The fabrication of integrated circuits (ICs) involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. The devices are interconnected, enabling the IC to perform the desired functions. Interconnections are formed by forming contacts and conductive lines in a dielectric layer using, for example, damascene techniques. A damascene structure, for example, includes a via or contact hole in a lower portion and a trench which is generally wider than the contact hole in an upper portion. The via serves as a contact to a device while the trench contains the conductive line for connecting the device to, for example, other devices.
As critical dimensions (CD) continue to shrink, the spacing between two metal lines reduces as well. Moreover, as the CD shrinks, it also provides challenges for liner deposition. Poor liner coverage will lead to the diffusion of the liner material, for example copper, to diffuse into the dielectric layer adjacent thereto. Therefore, time dependent dielectric breakdown (TDDB) has become an important reliability issue. For example, the destruction of the dielectric layer can cause interconnects to short, rendering the IC defective.
From the foregoing discussion, it is desirable to improve TDDB to increase IC reliability.